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Re: LSE Atomics

On 07.05.2020 05:59, Martin Husemann wrote:
> On Thu, May 07, 2020 at 01:13:21AM +0200, Tobias Nygren wrote:
>> Fetch sysctl machdep.cpu0.cpu_id (see usr.sbin/cpuctl/arch/aarch64.c)
>> Then test the ID_AA64ISAR0_EL1 register bits 23:20 for the value 0b0010.
> That doesn't sound safe (what if cpu0 and cpu$N disagree?)
> Martin

If there are CPU cores implementing different instructions in big.LITTLE
then the board is unsafe in SMP (e.g. ifunc logic can be broken and
trigger SIGILL).

FreeBSD recently added quirks to workaround problems with heterogeneous
machines with different types of CPU cores:


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