Re: RPi 4B+ ?

[mlelstv%serpens.de@localhost (Michael van Elst)]

michael.cheponis%gmail.com@localhost (Michael Cheponis) writes:

>Is there something I need to do to get evbarm to run on RPI 4B+ ?

Sure, write the necessary support code. :)

Currently I get up to the point where support for the new interrupt
controller would be helpful.

[   1.0000000] Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
[   1.0000000]     2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017,
[   1.0000000]     2018, 2019 The NetBSD Foundation, Inc.  All rights reserved.
[   1.0000000] Copyright (c) 1982, 1986, 1989, 1991, 1993
[   1.0000000]     The Regents of the University of California.  All rights reserved.

[   1.0000000] NetBSD 8.99.50 (EGGHED64) #134: Sun Jul 14 16:00:22 CEST 2019
[   1.0000000]  mlelstv@gossam:/home/netbsd-current/obj.evbarm64-el/home/netbsd-current/src/sys/arch4
[   1.0000000] total memory = 3940 MB
[   1.0000000] avail memory = 3799 MB
[   1.0000000] running cgd selftest aes-xts-256 aes-xts-512 done
[   1.0000000] armfdt0 (root)
[   1.0000000] simplebus0 at armfdt0: Raspberry Pi 4 Model B Rev 1.1
[   1.0000000] simplebus1 at simplebus0
[   1.0000000] simplebus2 at simplebus0
[   1.0000000] simplebus3 at simplebus0
[   1.0000000] cpus0 at simplebus0
[   1.0000000] simplebus4 at simplebus0
[   1.0000000] simplebus5 at simplebus0
[   1.0000000] cpu0 at cpus0: Cortex-A72 r0p3 (Cortex V8-A core)
[   1.0000000] cpu0: package 0, core 0, smt 0
[   1.0000000] cpu0: IC enabled, DC enabled, EL0/EL1 stack Alignment check enabled
[   1.0000000] cpu0: Cache Writeback Granule 16B, Exclusives Reservation Granule 16B
[   1.0000000] cpu0: Dcache line 64, Icache line 64
[   1.0000000] cpu0: L1 48KB/64B 3-way read-allocate PIPT Instruction cache
[   1.0000000] cpu0: L1 32KB/64B 2-way write-back read-allocate write-allocate PIPT Data cache
[   1.0000000] cpu0: L2 1024KB/64B 16-way write-back read-allocate write-allocate PIPT Unified cache
[   1.0000000] cpu0: revID=0x0, PMCv3, 4k table, 64k table, 16bit ASID
[   1.0000000] cpu0: auxID=0x10000, FP, CRC32, NEON, rounding, NaN propagation, denormals, 32x64bitR
[   1.0000000] cpu1 at cpus0: Cortex-A72 r0p3 (Cortex V8-A core)
[   1.0000000] cpu1: package 0, core 1, smt 0
[   1.0000000] cpu2 at cpus0: Cortex-A72 r0p3 (Cortex V8-A core)
[   1.0000000] cpu2: package 0, core 2, smt 0
[   1.0000000] cpu3 at cpus0: Cortex-A72 r0p3 (Cortex V8-A core)
[   1.0000000] cpu3: package 0, core 3, smt 0
[   1.0000000] simplebus6 at simplebus1
[   1.0000000] gic0 at simplebus1: GIC
[   1.0000000] fclock0 at simplebus2: 54000000 Hz fixed clock (osc)
[   1.0000000] bcmaux0 at simplebus1: couldn't get parent clock
[   1.0000000] fclock1 at simplebus2: 480000000 Hz fixed clock (otg)


-- 
-- 
                                Michael van Elst
Internet: mlelstv%serpens.de@localhost
                                "A potential Snark may lurk in every tree."