Re: Cortex-A9 boot problems with d-cache on Zynq

[Nick Hudson <nick.hudson%gmx.co.uk@localhost>]

> On 8 Jun 2019, at 12:53, Robert Swindells <rjs%fdy2.co.uk@localhost> wrote:
> 
> 
> Nick Hudson <nick.hudson%gmx.co.uk@localhost> wrote:
>>> On 02/06/2019 00:07, Robert Swindells wrote:
>>> 
>>> Alexander Nasonov <alnsn%yandex.ru@localhost> wrote:
>>>> Nick Hudson wrote:
>>>>> ...
>>>>> Can I convince you guys to work on FDTizing the ZYNQ7000 stuff? :)
>>>> 
>>>> Please tell me what I need to do. I added
>>> 
>>> The diffs that I posted a while ago compile, I don't think anything has
>>> changed in my tree since then.
>>> 
>>> Someone still needs to write a clock driver for it.
>>> 
>> 
>> I'll commit something to sys/arch/arm/xilinx so the FDTisation can
>> happen without breaking existing kernels
> 
> I don't feel that we should break an existing port, even if it is only
> for a short time.
> 
> If you are proposing to write a clock/reset driver then great.
> 
> I think it would be good to keep a separate PARALLELLA config even after
> the xilinx code is using FDT so that we don't need to update u-boot.

Sorry if I wasn’t clear. The point of the new directory is to keep the PARALLELLA (and other) config working

Nick