undefined instruction Re: TLS register access trapping failure on Orion

[Reinoud Zandijk <reinoud%NetBSD.org@localhost>]

Hi Matt, hi folks,

On Tue, Feb 14, 2012 at 08:57:54AM -0800, Matt Thomas wrote:
> On Feb 14, 2012, at 2:10 AM, Reinoud Zandijk wrote: Alas, it's not that
> simple.  You still to deal with setting the CONTEXT_ID register in
> cpu_setprivate and saving/restoring it in cpu_switchto.
> 
> reg 3 is easy since it's only ARMV6 and above.  reg 1 is a lot harder since
> only some armv5 have it, but not all.

Regretfully, I'll have to agree with this :-/ Testing on this ARMv5 machine,
it showed out that the context_id register is not readable in usermode and
gives a trap and that sucks. No win :(

Pity the access to these registers can't be programmed in the CPU so no luck
there either.

However, looking at the undefined instruction vector code its implemented
quite ..... slow! :-)

Although the ideas behind is are nice, i think the emulated instructions other
than say complext ones like FPE etc. ought to be done directly in undefined
instruction mode. That will only require a few instructions without all the
elaborate processor state save and load stuff and all the jumping around.

With regards,
Reinoud