Re: TLS register access trapping failure on Orion

[Reinoud Zandijk <reinoud%NetBSD.org@localhost>]

On Sat, Feb 11, 2012 at 10:52:06AM -0600, Jonathan A. Kollasch wrote:
> I'm running a recent -current evbarm on my Marvell Orion box (HP MV2120).
> All pthreaded processes segfault due to __lwp_getprivate_fast() returning
> a NULL pointer.  Further debugging shows that netbsd:cp15_trapper() never
> executes.
> 
> AFAICT Linux doesn't attempt to rely on unprivileged mrc/mrc trapping on
> pre-ARMv6.
> 
> Is there a plausible reason as to why this doesn't work?

well.... the ARM you are using is an ARM9 i.e. ARMv5 variant that has the
p15 copro register 13 support but also understands FCSE i.e. fast context
switching.

p15 copro regster 13 has 2 subregisters: 0 and 1. Other subregisters are not
defined! It *ought* to have created a unpriviledged mcr/mrc trap sure but for
some reason it doesnt. That could be considered a bug in the cpu.

So, if the ABI dictates we ought to use cp15 copro register 13 subregister 3
then we can use it. And if its zero, we can use subregister 1!.

From the ARM7 docs:
not found -> illegal instruction

From the ARM9 docs:
c13, 0, c0, 0 : RW FSCE PID register              *
c13, 0, c0, 1 : RW Context ID register            *
rest not defined, aparently treated as RAZ/WI

From the ARM11 docs:
c13, 0, c0, 0 : RW FCSE PID register              * **
c13, 0, c0, 1 : RW Context ID register            *
c13, 0, c0, 2 : user RW thread and processes ID
c13, 0, c0, 3 : user RO thread and processes ID
c13, 0, c0, 4 : privalidged only thread and process ID

From the Cortex-A15 docs:
c13, 0, c0, 0 : RAZ/WI RW FCSE PID register       * **
c13, 0, c0, 1 : RW Context ID register            *
c13, 0, c0, 2 : user RW thread and processes ID
c13, 0, c0, 3 : user RO thread and processes ID
c13, 0, c0, 4 : privalidged only thread and process ID
c13, 4, c0, 2 : Hyp Software Thread ID Register (??)

* register can be aparently written in user mode, bug or feature we can block?
** advised : register NOT to be used

Note that the Context ID register is also exported on the chippins for
external debugging. This has no consequence in normal boards.

1) old cpu's that don't understand c15 copro reg 13 will give illegal
instruction and can be emulated

2) armv5 cpu's that support FCSE have cp15 copro register 13 subregister 1 for
this

3) some armv6 cpu's completely ignore the subregister and have one register,
others are comparable to ARM11.

So basicly i came to the following code for getprivate_fast in mcontext.h:

-----------
static __inline void *
__lwp_getprivate_fast(void)
{
        void *rv;
        __asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(rv));
        __asm("cmp %0, #0" : "=r"(rv));
        __asm("mrceq p15, 0, %0, c13, c0, 1" : "=r"(rv));
        return rv;
}
------------

With regards,
Reinoud