[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
Re: TS-7200: time sync issues
In message: <200812100517.mBA5HFcG001471%ginger.cmf.nrl.navy.mil@localhost>
Ken Hornstein <kenh%cmf.nrl.navy.mil@localhost> writes:
: I'm not trying to be an obstinate bastard, honest.
Fair enough. Maybe I'm doing too much pattern patching to the
problems that I've had in the past... I've fought a lot of these
: I really do appreciate the help. I just can't convince myself that
: this is a frequency problem. My best guesses are that clock
: interrupts are blocked for too long when setting the TOD clock, or
: there is some strange arithmatic error when the time is set.
That was the other possible cause I listed... Either the timecounter
isn't ticking right due to math errors, input frequency errors or the
like, or the clock interrupts are being masked for some reason.
settimeofday just adjusts the boottime of the system, does some
housekeeping and then calls resettodr() at splclock(). splclock()
blocks interrupts. resettodr is a fancy wrapper around the chip
handle for the todr clock's todr_settime call. In eprtc.c we see
eprtc_settime which I think is what we're using on the TS-7200:
eprtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv)
struct eprtc_softc *sc = ch->cookie;;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, EP93XX_RTC_Load, tv->tv_sec);
which looks like a perfectly reasonable thing to do at splclock()
unless the bus write is blocked for a really insanely long time. So
unless there's some additional wrapper that I'm not seeing, I'm not
sure what to suggest.
Main Index |
Thread Index |