Re: timecounter TSC on Core i7

[Patrick Welche <prlw1%cam.ac.uk@localhost>]

On Tue, Sep 15, 2009 at 10:45:06PM +0200, Joerg Sonnenberger wrote:
> On Tue, Sep 15, 2009 at 01:26:13PM -0700, Paul Goyette wrote:
> > On Tue, 15 Sep 2009, Joerg Sonnenberger wrote:
> > 
> > >On Tue, Sep 15, 2009 at 11:27:32AM -0700, Paul Goyette wrote:
> > >>Would hpet be a better choice for timecounter?
> > >
> > >Not really. It is an order of magnitude slower. The best approach would
> > >be to port the TSC sync code to the lapic timer, which is known to be
> > >fixed frequency and also phase coherent, I think.
> > 
> > Hmm, I'm not even sure what a lapic is, or if/how it differs from
> > the ioapic mentioned in my dmesg!  :)
> 
> The IO-APIC(s) obtain(s) interrupts from device and forwards them to the
> local APIC bus. The L-APIC is part of the CPU/core and responsible for
> notifying the CPU of interupt requests from the IO-APIC or other
> L-APICs. The L-APIC has a local, per-core time interrupt and can also be
> used as time counter.

What you choose out of the following?

% grep timecounter dmesg.boot
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
timecounter: Timecounter "ACPI-Safe" frequency 3579545 Hz quality 900
timecounter: Timecounter "hpet0" frequency 14318179 Hz quality 2000
timecounter: Timecounter "ichlpcib0" frequency 3579545 Hz quality 1000
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0

(core 2 duo u9400, not core7)

Cheers,

Patrick