Re: kern/60144: virtio(4) cache coherence issue

["Jason Thorpe via gnats" <gnats-admin%NetBSD.org@localhost>]

The following reply was made to PR kern/60144; it has been noted by GNATS.

From: Jason Thorpe <thorpej%me.com@localhost>
To: gnats-bugs%netbsd.org@localhost
Cc: kern-bug-people%netbsd.org@localhost,
 gnats-admin%netbsd.org@localhost,
 netbsd-bugs%netbsd.org@localhost,
 isaki%pastel-flower.jp@localhost
Subject: Re: kern/60144: virtio(4) cache coherence issue
Date: Fri, 22 May 2026 08:31:20 -0400

 > On May 18, 2026, at 7:30=E2=80=AFPM, Taylor R Campbell via gnats =
 <gnats-admin%NetBSD.org@localhost> wrote:
 >=20
 > But on others -- such as m68k, mips, and armv<7 -- POSTREAD alone
 > isn't enough because it's a noop: these architectures assume that
 > after PREREAD, the driver doesn't load the memory in question until
 > the DMA read operation has completed, so flushing cached data in
 > PREREAD and doing nothing in POSTREAD is enough to ensure that the
 > driver's load isn't stale.
 
 This isn=E2=80=99t why.  The real reason is that the cache =
 implementation on some of these platforms does not have an =
 invalidate-without-writeback operation.
 
 -- thorpej