Re: kern/60144: virtio(4) cache coherence issue

[Jason Thorpe <thorpej%me.com@localhost>]

> On May 18, 2026, at 7:30 PM, Taylor R Campbell via gnats <gnats-admin%NetBSD.org@localhost> wrote:
> 
> But on others -- such as m68k, mips, and armv<7 -- POSTREAD alone
> isn't enough because it's a noop: these architectures assume that
> after PREREAD, the driver doesn't load the memory in question until
> the DMA read operation has completed, so flushing cached data in
> PREREAD and doing nothing in POSTREAD is enough to ensure that the
> driver's load isn't stale.

This isn’t why.  The real reason is that the cache implementation on some of these platforms does not have an invalidate-without-writeback operation.

-- thorpej