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Re: kern/60144: virtio(4) cache coherence issue
The following reply was made to PR kern/60144; it has been noted by GNATS.
From: Jason Thorpe <thorpej%me.com@localhost>
To: Tetsuya Isaki <isaki%pastel-flower.jp@localhost>
Cc: Taylor Campbell <riastradh%NetBSD.org@localhost>,
Jason Thorpe <thorpej%NetBSD.org@localhost>,
"netbsd-bugs%netbsd.org@localhost" <netbsd-bugs%NetBSD.org@localhost>,
"gnats-bugs%netbsd.org@localhost" <gnats-bugs%NetBSD.org@localhost>
Subject: Re: kern/60144: virtio(4) cache coherence issue
Date: Tue, 31 Mar 2026 06:24:36 -0700
> On Mar 31, 2026, at 3:34=E2=80=AFAM, Tetsuya Isaki =
<isaki%pastel-flower.jp@localhost> wrote:
>=20
> try to implement (and test) it.
> Or would someone take this?
I=E2=80=99ll be happy to implement it, and let you test it :-). It=E2=80=99=
s very trivial on 68030 since the cache is write-through.
-- thorpej
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