Re: kern/60144: virtio(4) cache coherence issue

["Jason Thorpe via gnats" <gnats-admin%NetBSD.org@localhost>]

The following reply was made to PR kern/60144; it has been noted by GNATS.

From: Jason Thorpe <thorpej%me.com@localhost>
To: gnats-bugs%netbsd.org@localhost
Cc: kern-bug-people%netbsd.org@localhost,
 gnats-admin%netbsd.org@localhost,
 netbsd-bugs%netbsd.org@localhost
Subject: Re: kern/60144: virtio(4) cache coherence issue
Date: Sun, 29 Mar 2026 21:39:43 -0700

 > On Mar 29, 2026, at 7:55=E2=80=AFPM, isaki%pastel-flower.jp@localhost via gnats =
 <gnats-admin%netbsd.org@localhost> wrote:
 >=20
 > And the following four results I observed also support this =
 assumption.
 > - qemu (68040, without cache impl.) could not reproduce.
 > - nono (68030, with cache impl.) could reproduce.
 > - nono (68040, without cache impl. yet)  could not reproduce.
 > - nono (68030, force disable data cache) could not reproduce.
 
 This actually brings up an interesting philosophical question: What does =
 DMA coherency mean in the context of virtio?
 
 If you think about whence virtio originated: virtualized devices, the =
 same machine, a guest <-> hypervisor communication channel.  It=E2=80=99s =
 all the same machine, it=E2=80=99s all the same memory.  If you think =
 about it, it=E2=80=99s inherently coherent, and modeling the cache =
 effects of a device doesn=E2=80=99t really seem aligned with what virtio =
 **fundamentally is**.
 
 Does that make sense?
 
 -- thorpej