port-sgimips/38932: sgimips bus_dmamap_sync() is incorrect

[Manuel Bouyer <bouyer%antioche.lip6.fr@localhost>]

>Number:         38932
>Category:       port-sgimips
>Synopsis:       sgimips bus_dmamap_sync() is incorrect
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    port-sgimips-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Tue Jun 10 14:55:00 +0000 2008
>Originator:     bouyer%antioche.lip6.fr@localhost
>Release:        current
>Organization:
>Environment:
System:
Architecture: sgimips
Machine: sgimips
>Description:
        The sgimips bus_dmamap_sync() do nothing for POSTREAD/POSTWRITE
        operations, assuming the PREREAD/PREWRITE operations have properly
        flushed/invalidated the cache. But cache invalidation should be done
        on POSTREAD operations too:
        if a driver loops waiting for a device to update a memory word
        by DMA (say, a status completion word of a DMA descriptor),
        the first read will properly fetch the value from memory, but
        subsequent ones will just get again the cached value, and the
        driver will never notice the updated word. If
        bus_dmamap_sync(POSTREAD) does a cache invalidation, the driver will
        see the updated value when the device writes it to memory.

>How-To-Repeat:
        code inspection.
>Fix:
        bus_dmamap_sync(POSTREAD) should do a cache invalidation.
        bus_dmamap_sync(PREREAD) should probably be turned to a NOP
        (we may still to cache invalidation in addition to cache flush
        in the case PREREAD|PREWRITE).