Subject: port-i386/36428: piixpcib boot hang on 4.0_BETA2
To: None <port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,>
From: None <doomwarriorx@gmail.com>
List: netbsd-bugs
Date: 06/02/2007 18:10:01
>Number:         36428
>Category:       port-i386
>Synopsis:       piixpcib boot hang on 4.0_BETA2
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    port-i386-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sat Jun 02 18:10:00 +0000 2007
>Originator:     Stephan Meisinger
>Release:        NetBSD 4.0 BETA2  ca. 2007-05-27
>Organization:
>Environment:
>Description:
piixpcib boot hang on 4.0_BETA2

For detailed descibed of my problem, please look here:
http://mail-index.netbsd.org/current-users/2007/05/30/0019.html

and later found also a Problem Report addressing the same issue on ThinkPad 390E with nearly the same hardware:
http://www.netbsd.org/cgi-bin/query-pr-single.pl?number=35313
>How-To-Repeat:
boot GENERIC_LAPTOP or any kernel with piixpcib on some laptops and proberbly also desktops/server with an unsupported Processor (e.g. Pentium II).
>Fix:
There are imho 3 possiblites for this fix.
1. don't match the device on unsupported processor types.
+ not error prone
+ work out of box with supported P-III
- normal isa bridge may not be configured, so no isa.
2. don't configure speedstep the device on unsupported processors
+ don't need normal isa bridge
+ work out of box with supported P-III
+ maximum of supported system with speedstep
- bogus default settings if gsic fail
- error prone because sc isn't configured.
3. don't configure speedstep if gsic call fail
+ on't need normal isa bridge
+ work out of box with supported P-III
- error prone because sc isn't configured.

I used version 2. My patch is against NetBSD-4.0 tree, but should also work with -current without modification

--- piixpcib.c.old      2007-06-02 18:54:11.000000000 +0200
+++ piixpcib.c  2007-06-02 18:52:09.000000000 +0200
@@ -226,6 +226,8 @@
        regs.EDX = PIIXPCIB_GSIC;
        bioscall(0x15, &regs);

+       aprint_debug("piixpcib: GSIC call EAX: 0x%x EBX: 0x%x ECX: 0x%x EDX: 0x%x\n", regs.EAX, regs.EBX, regs.ECX, regs.EDX);
+
        if (regs.EAX == PIIXPCIB_GSIC) {
                *sig = regs.EAX;
                *smicmd = regs.EBX & 0xff;
@@ -369,11 +371,28 @@
                sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff);
                sc->sc_flags = flags;
        } else {
-               /* setup some defaults */
-               sc->sc_smi_cmd = 0xb2;
-               sc->sc_smi_data = 0xb3;
-               sc->sc_command = 0x47534982;
-               sc->sc_flags = 0;
+
+               struct cpu_info *ci = &cpu_info_primary;
+
+               /* setup default values for supported processor types or bail out */
+               switch(ci->ci_signature) {
+                       case 0x680:
+                       case 0x681:
+                       case 0x683:
+                       case 0x686:
+                       case 0x6B0:
+                       case 0x6B1:
+                       case 0x6B4:
+                               /* setup some defaults */
+                               sc->sc_smi_cmd = 0xb2;
+                               sc->sc_smi_data = 0xb3;
+                               sc->sc_command = 0x47534982;
+                               sc->sc_flags = 0;
+                               break;
+                       default:
+                               aprint_verbose("%s: SpeedStep SMI not supported by processor\n", sc->sc_dev.dv_xname);
+                               return;
+               }
        }

        if (piixpcib_set_ownership(sc) != 0) {
@@ -460,4 +479,3 @@
 out:
        return (error);
 }