Re: radeon RS480 gets "Disabling GPU acceleration"

[coypu%SDF.ORG@localhost]

Hi, can you try this patch?
Thanks.

Index: radeon.h
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/radeon/radeon.h,v
retrieving revision 1.3
diff -u -r1.3 radeon.h
--- radeon.h	25 Jul 2014 12:47:18 -0000	1.3
+++ radeon.h	8 Aug 2016 15:25:28 -0000
@@ -607,6 +607,12 @@
 #define RADEON_GPU_PAGE_SHIFT 12
 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 
+#define RADEON_GART_PAGE_DUMMY  0
+#define RADEON_GART_PAGE_VALID  (1 << 0)
+#define RADEON_GART_PAGE_READ   (1 << 1)
+#define RADEON_GART_PAGE_WRITE  (1 << 2)
+#define RADEON_GART_PAGE_SNOOP  (1 << 3)
+
 struct radeon_gart {
 #ifdef __NetBSD__
 	bus_dma_segment_t		rg_table_seg;
Index: rs400.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/radeon/rs400.c,v
retrieving revision 1.3
diff -u -r1.3 rs400.c
--- rs400.c	26 Feb 2015 23:00:05 -0000	1.3
+++ rs400.c	8 Aug 2016 15:25:28 -0000
@@ -209,6 +209,7 @@
 	radeon_gart_table_ram_free(rdev);
 }
 
+#define RS400_PTE_UNSNOOPED (1 << 0)
 #define RS400_PTE_WRITEABLE (1 << 2)
 #define RS400_PTE_READABLE  (1 << 3)
 
@@ -222,9 +223,15 @@
 	}
 
 	entry = (lower_32_bits(addr) & PAGE_MASK) |
-		((upper_32_bits(addr) & 0xff) << 4) |
-		RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
+		((upper_32_bits(addr) & 0xff) << 4);
+	if (rdev->flags & RADEON_GART_PAGE_READ)
+		entry |= RS400_PTE_READABLE;
+	if (rdev->flags & RADEON_GART_PAGE_WRITE)
+		entry |= RS400_PTE_WRITEABLE;
+	if (!(rdev->flags & RADEON_GART_PAGE_SNOOP))
+		entry |= RS400_PTE_UNSNOOPED;
 	entry = cpu_to_le32(entry);
+
 	gtt[i] = entry;
 	return 0;
 }