Re: Memory alignment

[Sad Clouds <cryintothebluesky%googlemail.com@localhost>]

On Fri, 04 Dec 2009 10:14:52 -0500
Greg Troxel <gdt%ir.bbn.com@localhost> wrote:

> I think the real issue is that what you want is memory that is in
> different cache lines, not alignment.

Yes, so if the CPU cache line is 32 bytes, then every 32-bytes is
likely to go into a different cache line.

My machine is dual Pentium 3-S, which I think has 16K data + 16K
instruction cache, with 32-byte cache lines. So (16K / 32) = 512, which
means for direct mapped L1 cache, the same cache line would be evicted
every 512 bytes, hence the chance of collision would happen every 512
bytes.