On Wed, Jun 15, 2005 at 08:49:31PM +0200, Joerg Sonnenberger wrote:
> On Wed, Jun 15, 2005 at 07:50:28AM +0100, David Laight wrote:
> > However some architectures (eg sparc) do not give you the required 
> > sequencing of reads and writes - so any such attempt is doomed to failure.
> 
> Doesn't the Load-Link / Store Conditional allow exactly that?
> Sorry, didn't have time for assembly on my sparc book yet :)

I meant to imply that you had to use the cpu-dependant instructions
that do a locked read-write pair.  Using instructions that just a
'read' or a 'write' won't always work.

My sparc book only has ldstub and swap.

	David

-- 
David Laight: david@l8s.co.uk