On 2020/11/24 23:59, Jason Thorpe wrote:
On Nov 24, 2020, at 4:28 AM, Rin Okuyama <rokuyama.rk%gmail.com@localhost> wrote: CPU_CONTROL_SWP_ENABLE bit is missing for ARMv6. See cp15 c1 register bit definition on p.3-46 of ARM1176JZF-S Technical Reference Manual: | [10] F bit - Should Be Zero Also, it does not work for MULTIPROCESSOR in principle:Why?
Oops, it was wrong. ARM ARM "ARMv7-A and ARMv7-R edition", or, more
concisely, their web page says swp{,b} instructions on ARMv7 work for
MP system:
https://developer.arm.com/documentation/dht0008/a/swp-and-swpb/legacy-synchronization-instructions/limitations-of-swp-and-swpb
| Limitations of SWP and SWPB
| ...
| In a multi-core system, preventing access to main memory for all
| processors for the duration of a swap instruction can reduce
| overall system performance.
| ...
So, I guess that mrg@ disabled swp{,b} for MULTIPROCESSOR not because
instructions their-selves do not work, but because there are other
problems for ARMv5 userland on MP environment. As Robert suggested in
his previous message, multi-threaded applications for ARMv5 do not
work on MP system. See port-arm/55704 by myself:
http://gnats.netbsd.org/55704
Matthew, is this reason why you disabled them for MP kernel?
Thanks,
rin