make(1) variable expansion inconsistency

[der Mouse <mouse%Rodents-Montreal.ORG@localhost>]

Quite some time back, I wrote about problems building some software
because make(1) was overriding Makefile-set variables with
command-line-set variables only sometimes.

This is all on 4.0.1.

I believe I know when the "sometimes" is.  Consider this Makefile:

        V = makefile
        foo: xyz-${V}
        F:= xyz-${V}
        bar: ${F}
        xyz-cmd: .PHONY
                echo building xyz-cmd
        xyz-makefile: .PHONY
                echo building xyz-makefile

Now, consider "make V=cmd foo" and "make V=cmd bar".  They should be
identical, right?

Nope.

% make V=cmd foo
echo building xyz-cmd
building xyz-cmd
% make V=cmd bar
echo building xyz-makefile
building xyz-makefile
% 

It appears that variable expansion on dependency lines allows
command-line settings to override Makefile settings, but that variable
expansion when doing a var:=value setting doesn't.

Interestingly, 1.4T's make exhibits the same (mis?)behaviour on the
above test, though the build procedure that got me into this mess works
fine there - apparently something changed in /usr/share/mk between
versions (the build in question uses <bsd.lib.mk>) and exposed this.

A quick look at make's source doesn't make (ha) it obvious how to fix
this.  I'm going to be digging more, but if someone who knows make
better than I do would care to point me in the right direction (or,
better yet, fix it) that would be much appreciated.

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