> Do you have an example of the ARM warning?  I'm curious...

I was just trying to find it in my logs (and of course, I can't now :-)

It was the use of ldm and stm pairs generated from an inline asm block.  
The block contained something like

asm ("ldmia %4, {%0, %1, %2, %3}; stmia %5, {%0, %1, %2, %3}" : "=r" 
(tmp1), "=r" (tmp2), "=r" (tmp3), "=r" (tmp4) : "r" (src), "r" (dst) )

The format of an ldm instruction uses a bit-pattern for the register list, 
and the lowest numbered registers is stored at the lowest address.  So

  ldmia r0, {r1, r2, r3, r4}

is the same as

  ldmia r0, {r4, r3, r2, r1}

To help prevent the user falling over this, the assembler emits a warning 
if the registers aren't listed in ascending order.

However, gcc doesn't know that (and can't be forced to do it anyway) so it 
allocates random registers for the temporaries in the above pattern.

That doesn't matter, fortunately, since the stm that follows uses exactly 
the same register list, with exactly the same order (and the temporaries 
all die in the pattern).  So we get a warning that in this case happens to 
be irrelevant.

I've just realised that there is a way to write the above so that it will 
not trigger the warning.  It comes from wanting to support merged register 
lists (to help macro assembly programming).  If I write

	ldmia r0, {r4}+{r3}+{r2}+{r1}

then the assembler will accept that as written (it's the union of each of 
the register lists that ends up being loaded -- and similarly for the 
store).

So if you wanted to enable this for C files as well, we could (if the 
problem does still exist) fix the code.

R.