Subject: Re: Possible bug in arm32 strongarm optimisations.
To: Chris Gilbert <chris@buzzbee.freeserve.co.uk>
From: Mike Pumford <mpumford@mpc-data.co.uk>
List: tech-toolchain
Date: 10/25/2000 08:49:03
> Hi,
>
> I've been trying to build an arm32 kernel with the -mcpu=strongarm
> -mtune=strongarm.
>
> The problem I've had is that the podulebus doesn't get devices attaching
> properly. Anyway, after doing some rummaging around in the .s files from a
> kernel with and without the above options it seems that it's doing the
> following optimsation:
> turning:
> ldr r3, [r5, #6]
> mov r0, r3, lsr #16
> into
> ldrh r0, [r5, #4]
>
You have fallen into a slight trap of the RiscPC architecture. Although
the RiscPC has a StrongARM processor the memory interface does not
implement 16bit (halfword) transfers. Try the following options:
-march=armv3m -mtune=strongarm
This should keep the halfword instructions from being generated and
give you a working kernel.
Mike