On Tue, Dec 28, 1999 at 03:39:07PM -0500, Dan Winship wrote:
> > 	PowerPC does not require that floating point data be
> > word-aligned.  One can specify addresses to the individual byte.  FP loads
> > and stores that are not naturally aligned will be slower, but do
> > work.
> 
> Nope. From "The PowerPC Architecture", Book III, page 464:
> 
>   5.5.6 Alignment Interrupt
> 
>   An Alignment interrupt occurs when no higher priority exception
>   exists and the implementation cannot perform a storage access for
>   one of the reasons listed below.
> 
>   * The operand of a floating-point load or store is not word-aligned.
> 
>   * ...

  Note that each implementation is allowed to vary from the
architecture, as long as it doesn't break anything.  I can't
remember the exact terminology, but I think you get my drift...
:)

  In particular, Book IV for the 601 says that a floating-point
alignment exception only occurs if the address is in a
"non-memory-forced I/O controller interface segment", or if the
operand crosses a 4KB boundary or 256MB boundary, depending on
the translation mode settings.  Thus, from this quote, it
appears that the 601 will simply break the access into multiple
cache accesses.  (Ref.  5.4.6.2)

  Then, in Book IV for the 604, it states (underscores indicate
my emphasis):

    Note that the PowerPC architecture defines a wider range of
    conditions that _may_ cause an alignment exception than
    required in the 604.  In these cases, the 604 provides logic to
    handle these conditions without requiring the processor to
    invoke the alignment exception handler. (Ref. Table 4-2 in
    section 4.1)

  Later, it says that on the 604, non-word-aligned floating-point
accesses _do_ cause alignment exceptions, although "(t)he 604
provides hardware support for misaligned storage accesses for
other memory access instructions."  (Ref. 4.5.6)

  So, I would (naively) say that the generic PowerPC setting in a
compiler should be to use strict word alignment for float and
double accesses, but allow this to be overridden via the -mcpu=
flag or via another flag, for folks who know they will always be
running on a processor that can handle misalignment without
exceptions.  (There's a possible code density/I-cache argument for
using misaligned lfd, instead of two misaligned lwz.)

> ... and I get an alignment interrupt when it executes the stfd.

  Just wondering -- what processor did your system have?
Hopefully it's not a 601 -- if so, either I'm misinterpreting
the Book IV, or it's a documentation bug.  Most likely the
former.  :)

  Happy hacking.

  Brian Grayson, speaking as a guy who as a grad student
modified a PowerPC simulator so that it can handle misaligned
lfds, because gcc generates them.  :)