The documentation on the AMD website says the following about the
BSWP bit in CSR3:

	This bit is used to choose between big and little Endian modes of
operation.  When big Endian mode is slected, the controller will swap the
order of bytes on the AD bus during a data phase access to the FIFOs.
Byte wap only affects data transfers that involve the FIFOs.
Initialization block transfers are not affected by the setting of BSWP.
Descriptor transfgers are not affected by the setting of BSWP.  Note that
the byte ordering of the PCI bus is defined to be little Endian.  BSWP
should not be set to 1 when the controller is used in a PCI bus
application.

	Setting BSWP is not the solution, unfortunately.

David