I'm working on some support code for the AMD 79c973 LANCE chip
which uses MII to talk to its PHY (internal or external).
So I had to notice that there is already an entry for an AMD
OUI in dev/mii/miidevs which looks wrong and that there is generally
a giant mess in the interpretation of the OUIs.

It seems that the vendors do not agree in the way the 22 bits available
in the MII ID registers are mapped to the 3 bytes of their IEEE OUI.
Four out of our table (AMD, Intel, NatSemi, QualSemi) ise the bits
"as we would read them". Four other (ICS, Seeq, SIS, TI) have the
bits within a byte the other way - as they flow on the ethernet wire.
Level1 and Davicom are more different - Level1 has also the bytes
reversed, and Davicom is mysterious for me.

Probably the MII standard is not very clear about this - is there
someone who has a copy at hand?

This mess has caused some conflicts: On the '973, AMD uses its
real OUI (00-00-1a), but the table already contains an
00-60-6e for it (which is used on the '873 PHY chip). This in turn
matches the real OUI of Davicom.
(Well, "real" is under the assumption that the AMD/Intel/...
interpretation is correct.) Davicom uses another ID, according
to our table, which can't be explained that easily...

I'd say we should primarily list the real, IEEE registered
OUI in dev/mii/miidevs. The different ways to put them into
the MII ID registers should be dealt with in vendor specific
quirks.

The sad fact is that it is hard to identify MII chips -without
a special driver- in generic code, as eg PCI does.

So what I'd like to do is to change "miidevs" to list the
approved OUIs; ie:
oui AMD				0x00001a	Advanced Micro Devices
oui DAVICOM			0x00606e	Davicom Semiconductor
oui ICS				0x00a0be	Integrated Circuit Systems
oui INTEL			0x00aa00	Intel
oui LEVEL1			0x00207b	Level 1
oui NATSEMI			0x080017	National Semiconductor
oui QUALSEMI			0x006051	Quality Semiconductor
oui SEEQ			0x00a07d	Seeq
oui SIS				0x00e006	Silicon Integrated Systems
oui TI				0x080028	Texas Instruments

and to add special cases for chips which are diffent from the
"right" way. To find what's "right" some information from the
standard would be appreciated, but in doubt I'd stick with the
current MII_OUI() macro which reflects the AMD/Intel/... way.
The special cases could look more or less like:
/* in the 79c873, AMD uses another OUI which matches Davicom */
oui xxAMD			0x00606e	Advanced Micro Devices
/* some vendors have the register bits ordered as on the wire */
oui xxICS			0x00057d	Integrated Circuit Systems
/* Advanced Micro Devices PHYs */
model xxAMD 79C873		0x0000 Am79C873 10/100 media interface
model AMD 79c973phy		0x0036 Am79c973 internal PHY
model xxICS 1890		0x0002 ICS1890 10/100 media interface

Any comments / objections / clues?

best regards
Matthias