Re: bus_dma without bouncing

[Taylor R Campbell <riastradh%NetBSD.org@localhost>]

> Date: Tue, 27 Oct 2026 10:33:46 -0400 (EDT)
> From: Mouse <mouse%Rodents-Montreal.ORG@localhost>
> 
> > [1] [...].  But there are plenty of devices that require aligned
> >     addresses for DMA, such as Intel wireless cards which require 8-
> >     or 12-bit alignment.  [...]
> 
> What does 12-bit alignment even _mean_ on an 8-bit-addressing-unit
> machine (which IIRC includes everything NetBSD runs on)?  Does it
> differ from 3-byte alignment in any practical sense?  Do the interfaces
> even support alignment to other than a power of two?

By `k-bit alignment' I meant that the k low-order bits of the (byte)
addresses must be zero.  I.e., an address is 8-bit-aligned if it is an
integral multiple of 256, and an address is 12-bit-aligned if it is an
integral multiple of 4096, under this definition.

This constraint arises because the DMA registers don't even have space
for the low 8 (or 4 or 12 or whatever) bits:

   2046 	/* Set physical address of RX ring (256-byte aligned). */
   2047 	IWM_WRITE(sc,
   2048 	    IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG, sc->rxq.desc_dma.paddr >> 8);
   2049 
   2050 	/* Set physical address of RX status (16-byte aligned). */
   2051 	IWM_WRITE(sc,
   2052 	    IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG, sc->rxq.stat_dma.paddr >> 4);

https://nxr.NetBSD.org/xref/src/sys/dev/pci/if_iwm.c?r=1.94#2046