Re: Intel 82801H SATA interrupt issues

[Emmanuel Dreyfus <manu%netbsd.org@localhost>]

On Wed, Aug 28, 2024 at 12:28:24AM +0000, Emmanuel Dreyfus wrote:
> But that needs more tweaks, I found this:
> https://patchwork.ozlabs.org/project/linux-ide/patch/20110216090548.GQ5778%Redstar.dorchain.net@localhost/

This is on par with Intel documentation: ICH8 datasheet section 12.1.33
The PDF can be found here.
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/io-controller-hub-8-datasheet.pdf

We are told to change two bits in a PCI configuration register at 0x90. 
Linux does this by reading and writing a byte, we read and write pcireg_t.

I gave it a try by patching ahci match routine, but got no success so far.
Just to be sure: there is an endianness question here. Once I fetch 
pcireg_t at 0x90, the byte I am looking for is the MSB or the LSB?

-- 
Emmanuel Dreyfus
manu%netbsd.org@localhost