mpii_start() vs. mfii_start(): bus_space_write_raw_8(), bus_space_barrier()

[Edgar Fuß <ef%math.uni-bonn.de@localhost>]

I'm investigating timeout problems with my mpii(4) device (after the driver 
has been converted to MSI(-X). I'm trying to understand both 
sys/dev/pci/mpii.c and mfii.c since they adress the same hardware with 
different firmware.

Comparing mpii_start() with mfii_start(), I'm stumbling over a number of 
differences I don't understand (I've removed some debug statements from 
mpii_start()):


void
mpii_start(struct mpii_softc *sc, struct mpii_ccb *ccb)
{
	struct mpii_request_header	*rhp;
	struct mpii_request_descr	descr;
#if defined(__LP64__) && 0
	u_long				 *rdp = (u_long *)&descr;
#else
	u_int32_t			 *rdp = (u_int32_t *)&descr;
#endif

[...]
	bus_dmamap_sync(sc->sc_dmat, MPII_DMA_MAP(sc->sc_requests),
	    ccb->ccb_offset, sc->sc_request_size,
	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
[...]

#if defined(__LP64__) && 0
	bus_space_write_raw_8(sc->sc_iot, sc->sc_ioh,
	    MPII_REQ_DESCR_POST_LOW, *rdp);
#else
	mutex_enter(&sc->sc_req_mtx);
	bus_space_write_4(sc->sc_iot, sc->sc_ioh,
	    MPII_REQ_DESCR_POST_LOW, rdp[0]);
	bus_space_barrier(sc->sc_iot, sc->sc_ioh,
	    MPII_REQ_DESCR_POST_LOW, 8, BUS_SPACE_BARRIER_WRITE);

	bus_space_write_4(sc->sc_iot, sc->sc_ioh,
	    MPII_REQ_DESCR_POST_HIGH, rdp[1]);
	bus_space_barrier(sc->sc_iot, sc->sc_ioh,
	    MPII_REQ_DESCR_POST_LOW, 8, BUS_SPACE_BARRIER_WRITE);
	mutex_exit(&sc->sc_req_mtx);
#endif
}


static void
mfii_start(struct mfii_softc *sc, struct mfii_ccb *ccb)
{
	uint32_t *r = (uint32_t *)&ccb->ccb_req;
#if defined(__LP64__)
	uint64_t buf;
#endif

	bus_dmamap_sync(sc->sc_dmat, MFII_DMA_MAP(sc->sc_requests),
	    ccb->ccb_request_offset, MFII_REQUEST_SIZE,
	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

#if defined(__LP64__)
	buf = ((uint64_t)r[1] << 32) | r[0];
	bus_space_write_8(sc->sc_iot, sc->sc_ioh, MFI_IQPL, buf);
#else
	mutex_enter(&sc->sc_post_mtx);
	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MFI_IQPL, r[0]);
	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MFI_IQPH, r[1]);
	bus_space_barrier(sc->sc_iot, sc->sc_ioh,
	    MFI_IQPL, 8, BUS_SPACE_BARRIER_WRITE);
	mutex_exit(&sc->sc_post_mtx);
#endif
}


1. __LP64__ handling: Is the LP64 case simply an optimization or is it 
   safer on the relevant platforms?

2. bus_space_write_raw_8(): I can't find any description or references for 
   that function. Should that be bus_space_write_8()?

3. Single vs. double bus_space_barrier(): It strikes me as odd that 
   mpii_start() has a call between the two bus_space_write_4() calls while 
   mfii_start() hasn't. It also look suspicious to me that both calls use 
   MPII_REQ_DESCR_POST_LOW.

Can someone please enlighten me?