Re: timecounters

[Jason Thorpe <thorpej%me.com@localhost>]

> On Nov 14, 2021, at 4:49 PM, Joerg Sonnenberger <joerg%bec.de@localhost> wrote:
> 
>> x86 TSC: cycle count from CPU register. Very quick to read, but unreliable if 
>> CPU frequency changes because of power saving. Also each CPU has its own
>> value (how do we cope with that?)
> 
> It's even more complicated. For older x86 CPUs, different counts could
> go at different frequencies, but this was fixed around the Netburst era
> or so. That said, they frequently have issues when used in SMP systems.
> It's a high resolution timer.

This is handled correctly on Alpha now (fixed roughly 1 year ago with kern_cctr.c 1.11).  If the cycle counters are running at the same nominal frequency, the offset of the counter on the secondary CPUs is calibrated periodically (~once per second) relative to the primary CPU’s counter.  Alpha is the only port using that code at the moment, but there is nothing machine-dependent about it.

However, that code cannot deal with counters whose frequency changes, or counters that run at a different nominal frequency than the primary’s.

-- thorpej