Re: pci_intr_alloc() vs pci_intr_establish() - retry type?

[Masanobu SAITOH <msaitoh%execsw.org@localhost>]

On 2018/12/05 4:53, Jaromír Doleček wrote:
> I've now disabled MSI-X for ahcisata(4), need to figure what needs to
> be setup there.
>
> Le lun. 3 déc. 2018 à 22:41, Jared McNeill <jmcneill%invisible.ca@localhost> a écrit :
> > IIUC we don't actually have confirmation that ThunderX AHCI works yet..
> > Nick is having issues with his board.
>
> Okay - I misunderstood, thought it was confirmed working.
>
> The BAR used for Cavium is slightly suspicious. AHCI spec mentions
> (v1.3.1 section 2.4 Serial ATA Capability) 0x10 BAR as one of 'legacy'
> access methods. It specifically only talks about 0x24 as the proper
> BAR for AHCI, it doesn't mention option to have it elsewhere.
>
> Jaromir

 I suspect Serial ATA AHCI 1.2.1 specification page 111 has the hint.

 Figure 23: Port/CCC and MSI Message Mapping, Example 1
 Figure 24: Port and MSI Message Mapping, Example 2

I suspect MSI-X also assume this layout. pci_msix_alloc_map() might
be used.

 My SuperMicro A2SDi-H-TP4F's disk is connected to not channel 0
but channel 6. I also verified that GHC.MRSM is 0.
> ahcisata1 at pci0 dev 20 function 0: vendor 8086 product 19c2 (rev. 0x11)
> ahcisata1: interrupting at msix2 vec 0
> ahcisata1: 64-bit DMA
> ahcisata1: AHCI revision 1.31, 4 ports, 32 slots, CAP 0xc3349f43<EMS,PMD,SAM,ISS=0x3=Gen3,SCLO,SAL,SNCQ,S64A>
> XXXXX GHC = 80000002
> atabus8 at ahcisata1 channel 3
> atabus9 at ahcisata1 channel 4
> atabus10 at ahcisata1 channel 5
> atabus11 at ahcisata1 channel 6


--
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                SAITOH Masanobu (msaitoh%execsw.org@localhost
                                 msaitoh%netbsd.org@localhost)