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Fwd: L2 cache evbarm

I have a private port for an iMX31 based board which is itself based on evbarm. When I enable L2 cache in start.S the startup process freezes when I switch to the real L1 page table in initarm(). 

I wrote a custom flash boot program that loads the kernel with an initial ram disk. I enable L2 cache in the flash boot program and I see about a 15% to 20% improvement in load time; but when I start the kernel I do not enable L2 cache for the reason described above.

Can you give me some clues into the infrastructure that may need work to support L2 cache?

Frank Zerangue

Begin forwarded message:

Subject: Re: L2 cache evbarm
Date: December 8, 2014 at 7:30:07 PM CST

On Dec 8, 2014, at 4:58 PM, Frank Zerangue <> wrote:

Can anyone tell me what work would be needed to add L2 cache support to the evbarm port?

L2 cache support is very SoC specific.  Unless you tell us the target, we can't help you.
Chances are that the L2 cache is already supported.

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