Re: pserialize(9) vs. TAILQ

[Taylor R Campbell <campbell+netbsd-tech-kern%mumble.net@localhost>]

   Date: Thu, 20 Nov 2014 13:05:05 +0800
   From: Dennis Ferguson <dennis.c.ferguson%gmail.com@localhost>

   Adding a new barrier operation for this would only help if there
   were some determination to also go back and fix the code already
   written to use it, i.e. someone needs to decree that all code
   now needs to be written to theoretically run on an Alpha (the
   support would still only be theoretical since it is hard to
   find hardware which behaves like this to test on).

The attached patch adds membar_datadep_consumer with no changes needed
outside <sys/atomic.h> and alpha code (and any other CPU in the future
that might have a similarly relaxed memory ordering).  I have such
hardware, which I've been planning to use for exactly this purpose.

Writing membar_datadep_consumer makes it clear where interprocessor
communication is happening and where you must tread carefully, so I
see it as a net win for code clarity whether you want to run the code
on alpha or not.

Index: common/lib/libc/arch/alpha/atomic/membar_ops.S
===================================================================
RCS file: /cvsroot/src/common/lib/libc/arch/alpha/atomic/membar_ops.S,v
retrieving revision 1.6
diff -p -u -r1.6 membar_ops.S
--- common/lib/libc/arch/alpha/atomic/membar_ops.S	25 May 2008 15:56:11 -0000	1.6
+++ common/lib/libc/arch/alpha/atomic/membar_ops.S	20 Nov 2014 17:50:25 -0000
@@ -87,3 +87,5 @@ ATOMIC_OP_ALIAS(membar_exit,_membar_sync
 STRONG_ALIAS(_membar_exit,_membar_sync)
 ATOMIC_OP_ALIAS(membar_consumer,_membar_sync)
 STRONG_ALIAS(_membar_consumer,_membar_sync)
+ATOMIC_OP_ALIAS(membar_datadep_consumer,_membar_sync)
+STRONG_ALIAS(_membar_datadep_consumer,_membar_sync)
Index: lib/libc/atomic/membar_ops.3
===================================================================
RCS file: /cvsroot/src/lib/libc/atomic/membar_ops.3,v
retrieving revision 1.3
diff -p -u -r1.3 membar_ops.3
--- lib/libc/atomic/membar_ops.3	28 Apr 2011 11:56:26 -0000	1.3
+++ lib/libc/atomic/membar_ops.3	20 Nov 2014 17:53:23 -0000
@@ -27,7 +27,7 @@
 .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 .\" POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd February 11, 2007
+.Dd November 20, 2014
 .Dt MEMBAR_OPS 3
 .Os
 .Sh NAME
@@ -52,6 +52,8 @@
 .Ft void
 .Fn membar_consumer "void"
 .Ft void
+.Fn membar_datadep_consumer "void"
+.Ft void
 .Fn membar_sync "void"
 .Sh DESCRIPTION
 The
@@ -83,6 +85,40 @@ before any stores after the memory barri
 .It Fn membar_consumer
 All loads preceding the memory barrier will complete before any loads
 after the memory barrier complete.
+.It Fn membar_datadep_consumer
+Same as
+.Fn membar_consumer ,
+but limited to loads of addresses dependent on prior loads, or
+.Sq data-dependent
+loads:
+.Bd -literal -offset indent
+int **pp, *p, v;
+
+p = *pp;
+membar_datadep_consumer();
+v = *p;
+consume(v);
+.Ed
+.Pp
+Does not guarantee ordering of loads in branches, or
+.Sq control-dependent
+loads -- you must use
+.Fn membar_consumer
+instead:
+.Bd -literal -offset indent
+int *ok, *p, v;
+
+if (*ok) {
+	membar_consumer();
+	v = *p;
+	consume(v);
+}
+.Ed
+.Pp
+Most CPUs do not reorder data-dependent loads (i.e., most CPUs
+guarantee that cached values are not stale in that case), so
+.Fn membar_datadep_consumer
+is a no-op on those CPUs.
 .It Fn membar_sync
 All loads and stores preceding the memory barrier will complete and
 reach global visibility before any loads and stores after the memory
@@ -95,3 +131,7 @@ The
 .Nm membar_ops
 functions first appeared in
 .Nx 5.0 .
+The data-dependent load barrier,
+.Fn membar_datadep_consumer ,
+first appeared in
+.Nx 7.0 .
Index: sys/arch/alpha/include/types.h
===================================================================
RCS file: /cvsroot/src/sys/arch/alpha/include/types.h,v
retrieving revision 1.49
diff -p -u -r1.49 types.h
--- sys/arch/alpha/include/types.h	25 Jan 2012 18:09:13 -0000	1.49
+++ sys/arch/alpha/include/types.h	20 Nov 2014 17:50:47 -0000
@@ -70,6 +70,7 @@ typedef	volatile int		__cpu_simple_lock_
 
 #define	__HAVE_NEW_STYLE_BUS_H
 #define	__HAVE_ATOMIC_OPERATIONS
+#define	__HAVE_MEMBAR_DATADEP_CONSUMER
 #define	__HAVE_CPU_COUNTER
 #define	__HAVE_SYSCALL_INTERN
 #define	__HAVE_MINIMAL_EMUL
Index: sys/sys/atomic.h
===================================================================
RCS file: /cvsroot/src/sys/sys/atomic.h,v
retrieving revision 1.12
diff -p -u -r1.12 atomic.h
--- sys/sys/atomic.h	21 Feb 2014 15:52:53 -0000	1.12
+++ sys/sys/atomic.h	20 Nov 2014 17:50:53 -0000
@@ -156,6 +156,12 @@ void		membar_producer(void);
 void		membar_consumer(void);
 void		membar_sync(void);
 
+#ifdef	__HAVE_MEMBAR_DATADEP_CONSUMER
+void		membar_datadep_consumer(void);
+#else
+#define	membar_datadep_consumer()	((void)0)
+#endif
+
 __END_DECLS
 
 #endif /* ! _SYS_ATOMIC_H_ */