Re: RFC: IRQ affinity (aka interrupt routing)

[Kengo NAKAHARA <k-nakahara%iij.ad.jp@localhost>]

Hi,

(2014/08/20 18:46), Martin Husemann wrote:
> On Wed, Aug 20, 2014 at 06:38:35PM +0900, Kengo NAKAHARA wrote:
> > I use IRQ number to idetify interrupts. The number is shown "IRQ" column.
> > Actually, the value equals to struct intrsource.is_pin.
>
> Isn't a string (like in vmstat -i output) better?

I think IRQ number is better. Because it is short :)
Therefore, vmstat -iv output is differ little from IRQ number. For example,
here is the output of my machine
====================
interrupt                                     total     rate
TLB shootdown                                   732        0
cpu0 timer                                   151842      100
ioapic0 pin 9                                     0        0
ioapic0 pin 20                                    0        0
ioapic0 pin 21                                    0        0
ioapic0 pin 22                                    0        0
ioapic0 pin 23                                 1816        1
ioapic0 pin 19                                 1807        1
ioapic0 pin 18                                    0        0
ioapic0 pin 4                                     0        0
ioapic0 pin 3                                     0        0
Total                                        156197      103
====================
Currently, intrctl list does not show "TLB shootdown" and "cpu0 timer".
Furthermore, "ioapic0 pin 9" of vmstat -iv equals to "9" of intrctl list,
"ioapic0 pin 20" of vmstat -iv equals to "20" of intrctl list, and so on.

I think the problem of both vmstat -i output and IRQ number is that we cannot
immediately understand what device relates the line. So, intrctl list support
showing device name. For example, output of my machine with this patch is here.
    http://knakahara.github.io/patches/netbsd/support-rangeley-devices.patch
====================
 IRQ      CPU#00(+)       CPU#02(+)       CPU#04(+)       CPU#06(+)       
CPU#08(+)       CPU#10(+)       CPU#12(+)       CPU#14(+)
   3           0*              0               0               0               
0               0               0               0        unknown
   4           0*              0               0               0               
0               0               0               0        unknown
   9           0*              0               0               0               
0               0               0               0        unknown
  18           0*              0               0               0               
0               0               0               0        ichsmb0
  19        1777*              0               0               0               
0               0               0               0        ahcisata0, ahcisata1
  20           0*              0               0               0               
0               0               0               0        wm0
  21           0*              0               0               0               
0               0               0               0        wm1
  22           0*              0               0               0               
0               0               0               0        wm2
  23        1525*              0               0               0               
0               0               0               0        wm3, ehci0
====================
There is "unknown" devices yet, but it can show the devices name if the device
drivers use pci_intr_establish_xname() instead of pci_intr_establish().

I think it is easy to set affinity by IRQ number with above output.

> I am not sure we have a globally unique number available on all architectures
> to describe any interrupt.

I am not sure too. If the architecture does not have a unique number to
describe interrupts, it may be difficult for the architecture to  support
thisfeature. I do not think about the architectures other than x86 yet.
# I suppose SPARC can support this feature probably, but I don't know
# interrupts mechanism of other achitectures...

Thanks,

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Device Engineering Section,
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Kengo NAKAHARA <k-nakahara%iij.ad.jp@localhost>