Re: 4byte aligned com(4) and PCI_MAPREG_TYPE_MEM

[David Laight <david%l8s.co.uk@localhost>]

On Tue, Feb 11, 2014 at 09:21:30PM +0000, Eduardo Horvath wrote:
> > 
> > What you don't want to have is an API that swaps data in memory
> > (unless that is really what you want to do).
> > 
> > IIRC modern gcc detects uses of its internal byteswap function
> > that are related to memory read/write and uses the appropriate
> > byte-swapping memory access.
> > 
> > I can see the advantage of being able to do byteswap in the load/store
> > path, but sometimes that can't be arranged and a byteswap instruction
> > is very useful.
> 
> When do you ever really want to byte swap the contents of one register to 
> another register?  Byte swapping almost always involves I/O, which 
> means reading or writing memory or a device register.  In this case we 
> are specifically talking about DMA, in which case there is always a load 
> or store operation involved.

Quite often the structure of the code means that the value has already
been read into a register - so you are presented with a value in the
wrong byte order.

> > I really can't imagine implementing it being a big problem!
> 
> Yes, it a big problem.  For a 2 byte swap you need to do 2 shift 
> operations, one mask operation (if you're lucky) and one or operation.  
> Double that for a 4 byte swap.  And even if you argue that a dozen CPU 
> cycles here or there don't make much difference, the byte swap code is 
> replicated all over the place since the routines are macros, so you're 
> paying for it with your I$ bandwidth.

Sorry I meant a big problem for those designing cpus.
I know it is a pita in software.

About the only VHDL I've written is for a byteswap 'custom instruction'
for a soft-cpu. Done because a single cycle byteswap there was easier
than getting a ppc to use the byteswapping memory accesses for the
relevant fields.

        David

-- 
David Laight: david%l8s.co.uk@localhost