Re: "Hijacking" a PCU.

[David Laight <david%l8s.co.uk@localhost>]

On Sat, Dec 15, 2012 at 11:24:09AM -0800, Matt Thomas wrote:
> > 
> > On amd64 the safe area we currently have for SSE2 is 512 bytes.
> > Add support for the 256 AVX instructions and it increases to 832.
> > You really don't want to be allocating multiple such saved areas
> > (per lwp) on the off chance the kernel might want to use the registers.
> 
> Since this is MD, you only need to save the register your kernel
> MD code will be using.

> > 3) Saving and restoring a register may zero the high bits of an
> >   extended version of that register.
> 
> That's an md problem.

Since you are trying to sort out an MI solution you need to be aware
of the known MD problems - otherwise the framework won't work for it.

If an x86 program is using the 256bit AVX instructions, and some
kernel code wants to use one of the 128bit SSE registers, then the
kernel code has to save the 256 bit register, not the 128bit one.
(And next year, the register might be extended even further, requiring
different save/restore instructions.)

Effectively this means that a completely separate fpu save area is needed.
You can't just save a couple of registers on stack.

        David

-- 
David Laight: david%l8s.co.uk@localhost