Re: Musings on MSI

[Matt Thomas <matt%3am-software.com@localhost>]

On Aug 17, 2011, at 9:35 AM, David Young wrote:

> On Fri, Aug 05, 2011 at 03:09:53PM -0700, Matt Thomas wrote:
>> I'd like to keep the existing intr framework alone (mostly).  Here's a 
>> strawman for MI MSI support:
>> 
>> int pci_msi_request(const struct pci_attach_args *pa, pci_msi_handle_t 
>> *msihp, size_t nmsi, int capid);
>> 
>> msih in an opaque handle which is returned.
>> nmsi is the maximum number of msi that can be allocated.
>> capid is either 0 (either), PCI_CAP_MSI, or PCI_CAP_MSIX
>> 
>> returns an E* error.
>> 
>> int pci_msi_type(pci_chipset_tag_t pc, pci_msi_handle_t msih);
>> 
>> return the type of msi allocated (PCI_CAP_MSI or PCI_CAP_MSIX).  In the 
>> latter case MSI vectors may not be contiguous.
> 
> Does it matter to the driver whether or not the vectors are contiguous?
> Presumably there are no gaps in the available msirq?

MSIX doesn't matter, MSI it does.

>> size_t pci_msi_available(pci_chipset_tag_t pc, pci_msi_handle_t msih);
>> 
>> returns the number of MSIs allocated (or currently free).
> 
> You mean, the minimum of the number of MSIs allocated by
> pci_msi_request(), and the number of MSIs pci_msi_establish()'d but not
> pci_msi_free()'d ?

No.  The number of msirqs that can used for pci_msi_establish.

>> void * pci_msi_establish(pci_chipset_tag_t pc, pci_msi_handle_t msih, 
>>   size_t msirq, int level, int (*handler)(void *), void *arg);
>> 
>> establishes the Nth (msirq) MSI (appropriately updating the MSIX vector table
>> if needed).  More than one handler may be established on a single MSI.
>> 
>> void pci_msi_disestablish(pci_chipset_tag_t pc, void *ih);
>> 
>> Disestablishes but does not free the MSI.
> 
> You mean, pci_msi_disestablish() does not free to the MSI handle's pool?
> Why not?

It does.  But not to the system pool.   pci_msi_free does that.

> It may help to see an example of how this is used.
> 
> It occurs to me that MSI/MSI-X establishment may need to modify bus
> windows, IOMMU mappings, et cetera.

Depends on the platform but that's transparent to the user.   The underlying MD 
pci bus code should do that.