Re: Non power-of-two cache sizes and page colouring

To: Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>
Subject: Re: Non power-of-two cache sizes and page colouring
From: Simon Burge <simonb%NetBSD.org@localhost>
Date: Fri, 18 Apr 2008 02:44:58 +1000

Izumi Tsutsui wrote:

> BTW, is it really 2*N way set associative?
> Isn't it 3*N way set associative?
> i.e. isn't it 24 way rather than 16 way?

It's reported as:

   cpu0: L2 cache 6 MB 64B/line 16-way

but I can't find a mention in the Intel datasheets that it really is
16-way and not 24-way.  Digging further did show that apparently it's
6MB per "core pair" and 12MB for the chip in total.  Note that that
clears anything up :-)

Cheers,
Simon.

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