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On Sat, Jun 30, 2007 at 03:21:29AM +0800, Brandon Lee wrote:
> HI Manuel,
> 
> Yes the iso from your ftp works for the BCM5754 NIC.  Attached is the
> dmesg log. 

Cool. Were you able to ifconfig it and send/receive packets ?
Getting it in dmesg is one thing, getting it to talk to network is another :)

> Are you able to provide me a patch for this?

See attached file. If you confirm it can talk to the network, I'll
commit it to current and request pullups.

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
     NetBSD: 26 ans d'experience feront toujours la difference
--

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Index: if_bge.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_bge.c,v
retrieving revision 1.131
diff -u -r1.131 if_bge.c
--- if_bge.c	9 Jun 2007 21:42:33 -0000	1.131
+++ if_bge.c	29 Jun 2007 19:29:16 -0000
@@ -277,6 +277,8 @@
 #define BGE_IS_5750_OR_BEYOND(sc)  \
 	(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \
 	 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \
+	 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \
+	 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \
 	 BGE_IS_5714_FAMILY(sc) )
 
 #define BGE_IS_5705_OR_BEYOND(sc)  \
@@ -1772,8 +1774,14 @@
 	}
 
 	/* Turn on write DMA state machine */
-	CSR_WRITE_4(sc, BGE_WDMA_MODE,
-	    BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
+	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
+	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
+		/* host coalescing bug fix, from FreeBSD */
+		CSR_WRITE_4(sc, BGE_WDMA_MODE,
+		    BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS | (1 << 29));
+	else
+		CSR_WRITE_4(sc, BGE_WDMA_MODE,
+		    BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
 
 	/* Turn on read DMA state machine */
 	{
@@ -1990,6 +1998,27 @@
 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
 	  "BCM5752 A2" },
 
+	{ BGE_CHIPID_BCM5755_A0,
+	  BGE_QUIRK_5705_CORE,
+	  "BCM5754/5787 A0" },
+	{ BGE_CHIPID_BCM5755_A1,
+	  BGE_QUIRK_5705_CORE,
+	  "BCM5754/5787 A1" },
+	{ BGE_CHIPID_BCM5755_A2,
+	  BGE_QUIRK_5705_CORE,
+	  "BCM5754/5787 A2" },
+
+	/* 5754 and 5787 share the same ASIC ID */
+	{ BGE_CHIPID_BCM5787_A0,
+	  BGE_QUIRK_5705_CORE,
+	  "BCM5754/5787 A0" },
+	{ BGE_CHIPID_BCM5787_A1,
+	  BGE_QUIRK_5705_CORE,
+	  "BCM5754/5787 A1" },
+	{ BGE_CHIPID_BCM5787_A2,
+	  BGE_QUIRK_5705_CORE,
+	  "BCM5754/5787 A2" },
+
 	{ 0, 0, NULL }
 };
 
@@ -2039,6 +2068,14 @@
 	  BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE,
 	  "unknown BCM5780" },
 
+	{ BGE_ASICREV_BCM5755,
+	  BGE_QUIRK_5705_CORE,
+	  "unknown BCM5755" },
+	/* 5754 and 5787 share the same ASIC ID */
+	{ BGE_ASICREV_BCM5787,
+	  BGE_QUIRK_5705_CORE,
+	  "unknown BCM5754/5787" },
+
 	{ 0,
 	  0,
 	  NULL }
@@ -2209,6 +2246,16 @@
 	  "Broadcom BCM5753M Gigabit Ethernet",
 	  },
 
+	{ PCI_VENDOR_BROADCOM,
+	  PCI_PRODUCT_BROADCOM_BCM5754,
+	  "Broadcom BCM5754 Gigabit Ethernet",
+	  },
+
+	{ PCI_VENDOR_BROADCOM,
+	  PCI_PRODUCT_BROADCOM_BCM5754M,
+	  "Broadcom BCM5754M Gigabit Ethernet",
+	  },
+
    	{ PCI_VENDOR_BROADCOM,
 	  PCI_PRODUCT_BROADCOM_BCM5780,
 	  "Broadcom BCM5780 Gigabit Ethernet",
@@ -2739,7 +2786,9 @@
 	 * Disable the firmware fastboot feature on 5752 ASIC
 	 * to avoid firmware timeout.
 	 */
-	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752)
+	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
+	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
+	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
 		CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
 
 	val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1);
Index: if_bgereg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_bgereg.h,v
retrieving revision 1.42
diff -u -r1.42 if_bgereg.h
--- if_bgereg.h	18 May 2007 22:30:24 -0000	1.42
+++ if_bgereg.h	29 Jun 2007 19:29:16 -0000
@@ -277,6 +277,12 @@
 #define BGE_CHIPID_BCM5715_A3		0x90030000
 #define BGE_CHIPID_BCM5787_A2		0xb0020000
 #define BGE_CHIPID_BCM5906_A1		0xc0010000
+#define BGE_CHIPID_BCM5755_A0		0xa0000000
+#define BGE_CHIPID_BCM5755_A1		0xa0010000
+#define BGE_CHIPID_BCM5755_A2		0xa0020000
+#define BGE_CHIPID_BCM5787_A0		0xb0000000
+#define BGE_CHIPID_BCM5787_A1		0xb0010000
+#define BGE_CHIPID_BCM5787_A2		0xb0020000
 
 /* shorthand one */
 #define BGE_ASICREV(x)			((x) >> 28)
@@ -294,6 +300,8 @@
 #define BGE_ASICREV_BCM5755		0x0a
 #define BGE_ASICREV_BCM5787		0x0b
 #define BGE_ASICREV_BCM5706		0x0c
+#define BGE_ASICREV_BCM5755		0x0a
+#define BGE_ASICREV_BCM5787		0x0b
 
 /* chip revisions */
 #define BGE_CHIPREV(x)			((x) >> 24)

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