Subject: Re: The radeon framebuffer device panics init (on i386)
To: Michael Lorenz <macallan@netbsd.org>
From: Vincent <10.50@free.fr>
List: tech-kern
Date: 12/19/2006 21:35:51
Hi there!

Ok, I patched the file in order to not call radeon_loadbios when the 
option flag RADEON_BIOS_INIT is inactive. It works. At least, very 
partly: the system goes up fine, but I lose any video output at the time 
the radeonfb driver is attached, so I assume the code, founding no 
suitable BIOS (the patch I wrote sets cf->cf_biossz to 0) makes (wrong) 
guesses about the default configuration.

If it serves any purpose, you'll find appended the dmesg output.

Is there a way to compare this dmesg log to the Xorg.log and especially 
the output of the radeon driver?

Thanks
Vincent

radeonfb0 at pci1 dev 0 function 0: vendor 0x1002 product 0x4c57
RADEON_BIOS_4_SCRATCH = 01000004
RADEON_FP_GEN_CNTL = 01430000
RADEON_FP2_GEN_CNTL = 00000008
RADEON_TMDS_CNTL = 01000000
RADEON_TMDS_TRANSMITTER_CNTL = 10000082
RADEON_TMDS_PLL_CNTL = 00000a1b
RADEON_LVDS_GEN_CNTL = 083dffa1
RADEON_FP_HORZ_STRETCH = 0e7f09ff
RADEON_FP_VERT_STRETCH = 0e2ff855
radeonfb0: No video BIOS, using default clocks
no suitable DFP table present
TMDS_PLL dot clock 15000 pll a1b
TMDS_PLL dot clock -1 pll a3f
TMDS_PLL dot clock 0 pll 0
TMDS_PLL dot clock 0 pll 0
radeonfb0: refclk = 27.000 MHz, refdiv = 12 minpll = 125000, maxpll = 350000
No connector info in BIOS!
Port #0:
     conn = 4
     ddc = 2
     dac = 1
     tmds = 0
Port #1:
     conn = 2
     ddc = 3
     dac = 0
     tmds = 1
aperbase = 2281701376
RADEON_MC_FB_LOCATION = 8bff8800
RADEON_MC_AGP_LOCATION = 8bff8c00
RADEON_DAC_CNTL2 = 00000000
RADEON_DAC_CNTL2 = 00000000
RADEON_DAC_CNTL2 = 00000003
RADEON_DISP_HW_DEBUG = 00020020
RADEON_DAC_CNTL = ff000102
RADEON_TV_DAC_CNTL = 00280203
radeonfb0: 64 MB aperture at 0x88000000, 64 KB registers at 0x80380000
dual crtcs!
radeonfb0: display 0: initial virtual resolution 640x480 at 32 bpp
radeonfb0: port 0: physical 1024x768 60Hz
radeonfb0: port 1: physical 1024x768 60Hz
fpbtr = 0xcadf8000
init engine
init screen called, existing 1
CRTC_GEN_CNTL = 03000600
RADEON_CRTC_EXT_CNTL = 00008048
CRTC_H_TOTAL_DISP = 007f00a7
FP_H_TOTAL_DISP = 007f00a7
CRTC_H_SYNC_STRT_WID = 00910418
FP_H_SYNC_STRT_WID = 00910418
CRTC_V_TOTAL_DISP = 02ff0325
FP_V_TOTAL_DISP = 02ff0325
CRTC_V_SYNC_STRT_WID = 00860302
CRTC_V_TOTAL_DISP = 02ff0325
FP_V_TOTAL_DISP = 02ff0325
CRTC_V_SYNC_STRT_WID = 00860302
FP_V_SYNC_STRT_WID = 00860302
dot clock: 65000
outfreq: 130000
post divider: 2 (mask 10000)
feedback divider: 58
RADEON_PPLL_REF_DIV = 0000000c
RADEON_PPLL_CNTL = 0000bc30
RADEON_CRTC_MORE_CNTL = 00000000
RADEON_CRTC_EXT_CNTL = 0d008048
RADEON_CRTC_GEN_CNTL = 03000600
RADEON_CLOCK_CNTL_INDEX = 00000000
CRTC2_GEN_CNTL = 02000680
RADEON_CRTC_EXT_CNTL = 0d008048
CRTC2_H_TOTAL_DISP = 007f00a7
FP_H2_TOTAL_DISP = 007f00a7
CRTC2_H_SYNC_STRT_WID = 00910418
FP_H2_SYNC_STRT_WID = 00910418
CRTC2_V_TOTAL_DISP = 02ff0325
FP_V2_TOTAL_DISP = 02ff0325
CRTC2_V_SYNC_STRT_WID = 00860302
FP_V2_SYNC_STRT_WID = 00860302
dot clock: 65000
outfreq: 130000
post divider: 2 (mask 10000)
feedback divider: 58
RADEON_CRTC_MORE_CNTL = 00000000
RADEON_CRTC2_GEN_CNTL = 02000680
wsdisplay0 at radeonfb0 kbdmux 1: console (fb, vt100 emulation), using 
wskbd0
wsmux1: connecting to wsdisplay0
init screen called, existing 0
init screen called, existing 0
wsdisplay0: screen 1-2 added (fb, vt100 emulation)
RADEON_FP_GEN_CNTL = 01430085
RADEON_FP2_GEN_CNTL = 0000200c