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Hi,

On Fri, Jun 03, 2005 at 03:39:10PM -0700, Jonathan Stone wrote:

> Back in the days of 4BSD on a VAX, processor IPLs were effectively a
> counter, not bitfields; so _all_ SPLs that mapped to distinct CPU
> prioities always implicitly masked all lower SPLs.

That's still the case for some of our architectures, e.g. m68k and probably
VAX (although I'm not sure about VAX, especially what VAX does for SMP
machines).

As we're talking about MI code here (I think), we should be aware of this.

Regards,
	-is

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Content-Type: application/pgp-signature
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-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.3 (NetBSD)

iD8DBQFCoV9GN4tiz3B8hB0RAlVHAKCiBdZlecd33Vc3UUeSY1IeGJsfhgCfcVcm
sfJAE78hlPXmq/jcR1gSA4o=
=hrWA
-----END PGP SIGNATURE-----

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