I've been thinking for the last few days about how I might implement 
support for the VFP floating-point unit on some ARM devices and there are 
a number of questions that I've been unable to resolve by studying the 
support code for other CPUs.  I wonder if anybody can provide some insight.

1) Do other cores have imprecise faults? (By 'fault' I mean to raise an 
exception or to do software emulation of the operation because the values 
in question can't be determined by the hardware.  By imprecise I mean that 
the current PC value does not point to the instruction and that it isn't a 
simple permutation of that value to get the address of the faulting 
instruction.)  I think the answer to this one must be 'yes', but I'd like 
to see confirmation from someone more familiar with the other 
architectures.

2) If so, can the PC value of the faulting instruction always be 
recovered?  If not, what information is passed to a SIGFPE handler?  On 
the VFP the instruction opcode is known, but not the address of the 
fault-raising instruction.  I guess it would be possible to write the 
opcode to memory somewhere and point the siginfo frame at that; but is 
there a standard procedure for doing this?

3) What happens if there is a pending fault and the process gets stopped 
in GDB before we can handle it?  Do we just lie to the user and pretend 
the floating point state is correct? or do we somehow try to stabilize the 
register values before we pass them to GDB?  If the latter, what if there 
are multiple outstanding operations and one (or more) would need to raise 
SIGFPE?

Any assistance would be greatly appreciated.

R.