Re: is anyone maintaining hifn(4)?

[emily ingalls <emily@ingalls.rocks>]

i accidentally copied too much into that last email - just for clarity, here's the diff alone 

diff -u -r a/sys/dev/pci/hifn7751.c b/sys/dev/pci/hifn7751.c
--- a/sys/dev/pci/hifn7751.c    2018-12-27 06:03:54.000000000 -0800
+++ b/sys/dev/pci/hifn7751.c    2021-07-17 23:42:13.371790047 -0700
@@ -1073,6 +1073,17 @@
               WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
                   HIFN_PUCNFG_TCALLPHASES |
                   HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
+               /* per datasheet: set PLL speed and charge current,
+                * and turn on the PLL bypass */
+               WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956_INIT);
+               /* then, wait at least 10ms for the PLL to lock */
+               kpause("hifnpll", false, mstohz(10), NULL);
+               /* then, disable PLL bypass */
+               WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956_INIT2);
+               /* pause again for good measure */
+               kpause("hifnpll", false, mstohz(10), NULL);
+               /* write the final PLL config value, with packet engine and
+                * key engine set to use the PLL output */
               WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956);
       } else {
               WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
diff -u -r a/sys/dev/pci/hifn7751reg.h b/sys/dev/pci/hifn7751reg.h
--- a/sys/dev/pci/hifn7751reg.h 2005-12-11 04:22:49.000000000 -0800
+++ b/sys/dev/pci/hifn7751reg.h 2021-07-17 23:42:13.372045735 -0700
@@ -361,7 +361,16 @@
/*
 * PLL config register
 */
-#define        HIFN_PLL_7956           0x00001d18      /* 7956 PLL config value */
+
+/* 7956 PLL config values 
+ *
+ * set PLL to use onboard reference, rather than a potentially
+ * unknown and unstable bus clock. setting PLL correctly requires
+ * three steps. 
+ */
+#define HIFN_PLL_7956_INIT     0x00001c03 /* initial state, setting pll clock source */
+#define HIFN_PLL_7956_INIT2    0x00001c01 /* after PLL stabilizes, clear PLL bypass bit */
+#define        HIFN_PLL_7956           0x00001c19 /* set packet and key engines to use PLL */

/*********************************************************************
 * Structs for board commands
hakase$ diff -u -r a/sys/dev/pci b/sys/dev/pci 
diff -u -r a/sys/dev/pci/hifn7751.c b/sys/dev/pci/hifn7751.c
--- a/sys/dev/pci/hifn7751.c    2018-12-27 06:03:54.000000000 -0800
+++ b/sys/dev/pci/hifn7751.c    2021-07-17 23:42:13.371790047 -0700
@@ -1073,6 +1073,17 @@
               WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
                   HIFN_PUCNFG_TCALLPHASES |
                   HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
+               /* per datasheet: set PLL speed and charge current,
+                * and turn on the PLL bypass */
+               WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956_INIT);
+               /* then, wait at least 10ms for the PLL to lock */
+               kpause("hifnpll", false, mstohz(10), NULL);
+               /* then, disable PLL bypass */
+               WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956_INIT2);
+               /* pause again for good measure */
+               kpause("hifnpll", false, mstohz(10), NULL);
+               /* write the final PLL config value, with packet engine and
+                * key engine set to use the PLL output */
               WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956);
       } else {
               WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
diff -u -r a/sys/dev/pci/hifn7751reg.h b/sys/dev/pci/hifn7751reg.h
--- a/sys/dev/pci/hifn7751reg.h 2005-12-11 04:22:49.000000000 -0800
+++ b/sys/dev/pci/hifn7751reg.h 2021-07-17 23:42:13.372045735 -0700
@@ -361,7 +361,16 @@
/*
 * PLL config register
 */
-#define        HIFN_PLL_7956           0x00001d18      /* 7956 PLL config value */
+
+/* 7956 PLL config values 
+ *
+ * set PLL to use onboard reference, rather than a potentially
+ * unknown and unstable bus clock. setting PLL correctly requires
+ * three steps. 
+ */
+#define HIFN_PLL_7956_INIT     0x00001c03 /* initial state, setting pll clock source */
+#define HIFN_PLL_7956_INIT2    0x00001c01 /* after PLL stabilizes, clear PLL bypass bit */
+#define        HIFN_PLL_7956           0x00001c19 /* set packet and key engines to use PLL */

/*********************************************************************
 * Structs for board commands