CVS commit: src/sys/arch/evbmips

["Thor Lancelot Simon" <tls%netbsd.org@localhost>]

Module Name:    src
Committed By:   tls
Date:           Sun May 10 14:56:40 UTC 2026

Modified Files:
        src/sys/arch/evbmips/conf: MALTA
        src/sys/arch/evbmips/malta: machdep.c malta_bus_io.c malta_bus_mem.c
            malta_intr.c
        src/sys/arch/evbmips/malta/dev: gt.c mainbus.c
        src/sys/arch/evbmips/malta/pci: pcib.c

Log Message:
Address problems with MIPS Malta platform code found running under QEMU.

QEMU's "malta" system emulates a MIPS Malta with the Gallileo host bridge
and 32-bit or 64-bit CPUs of either endianness.  It is one of the only
working QEMU system-level emulations that could run NetBSD with all
combinations of endianness and address size.  After fixes to QEMU over the
past several years, NetBSD has been unable to use the emulated PCI bus in
big-endian and 64-bit configurations.

No actual Malta hardware with any Gallileo-based CPU card could be found
for testing.  These changes have been checked against the databook and
some limited checking of the relevant QEMU changes (which seem to have
mostly come from former MIPS employees) was also performed.

Changes:
1. The GT-64120 host bridge _does_ byte-swap access to other PCI targets,
   but _does not_ byte-swap access to itself (bus 0, device 0).  QEMU
   evidently used to get this wrong, but, I confirmed with the databook.
   This means we need to manually byte-swap a bunch of access to the
   bridge's own regs, or when running big-endian, PCI just basically does
   not work (no devices found; interrupt handling not working anyway).

2. Remove a hardcoded #undef YAMON_IRQ_MAP_BAD and change the PCI IRQ
   mappings we then install to better match QEMU.  This allows use of
   options YAMON_IRQ_MAP_BAD and PCI_NETBSD_CONFIGURE to ensure interrupts
   are mapped properly when we are booted with qemu -kernel instead of
   from a disk image.  This also involved a small change to Malta's copy
   of the pcib driver, which I should note includes a hardcoded constant
   0x60 for the Intel PIIX's PIRQRC register.  This must be defined in some
   header file, right?  I can't find it.

3. Malta's bus space does not define CHIP_LITTLE_ENDIAN.  If the QEMU
   behavior is correct (DEVICE_LITTLE_ENDIAN: automatically swap multibyte
   access) then without this I can't see how it possibly ever worked in
   big endian mode either on QEMU or physical hardware.  QEMU seems to
   have relatively recently fixed this, so if it worked on QEMU before, it
   is likely because QEMU was broken.

4. QEMU's YAMON emulation sets a bogus timer frequency.  This fix is easy:
   just always run the timer calibration.

5. Make the PCI_NETBSD_CONFIGURE code work properly on Malta by conforming
   it to the Galileo databook and the observed behavior of QEMU and (per
   comments in other people's code) real YAMON: BAR allocation should start
   at MALTA_PCIMEM_2_BASE, not MALTA_PCIMEM1_BASE.

6. Add options PCI_NETBSD_CONFIGURE and YAMON_IRQ_MAP_BAD to the MALTA
   kernel (and thus, by inclusion, to the MALTA64 kernel).


To generate a diff of this commit:
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/evbmips/conf/MALTA
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/evbmips/malta/machdep.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbmips/malta/malta_bus_io.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbmips/malta/malta_bus_mem.c
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/evbmips/malta/malta_intr.c
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/evbmips/malta/dev/gt.c
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/evbmips/malta/dev/mainbus.c
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/evbmips/malta/pci/pcib.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.