CVS commit: [netbsd-11] src/sys/arch/arm

["Martin Husemann" <martin%netbsd.org@localhost>]

Module Name:    src
Committed By:   martin
Date:           Wed Oct  1 16:41:13 UTC 2025

Modified Files:
        src/sys/arch/arm/arm32 [netbsd-11]: bus_dma.c
        src/sys/arch/arm/include [netbsd-11]: cpufunc.h

Log Message:
Pull up following revision(s) (requested by skrll in ticket #40):

        sys/arch/arm/include/cpufunc.h: revision 1.92
        sys/arch/arm/arm32/bus_dma.c: revision 1.150

arm: Adjust barriers issued in bus_dmamap_sync for the coherent case.
PR/59654

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.
These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

A new indrection is introduced to deal with the differencs in barrier
(dsb) options between Arm V8 and V7, the lack of options in Arm V6,
and the need to use cpu_drain_writebuf for all other earlier versions.

The Arm V8 Net change is:
op                      old                     new
---------------------   ----------------------  ------------
PREREAD                 none                    dsb(osh)
PREWRITE                cpu_drain_writebuf      dsb(oshst)
PREREAD|PREWRITE        cpu_drain_writebuf      dsb(osh)
POSTREAD                cpu_drain_writebuf      dsb(oshld)
POSTWRITE               none                    none
POSTREAD|POSTWRITE      cpu_drain_writebuf      dsb(oshld)
where cpu_drain_writebuf is a dsb(sy) or CPU equivalent.


To generate a diff of this commit:
cvs rdiff -u -r1.149 -r1.149.2.1 src/sys/arch/arm/arm32/bus_dma.c
cvs rdiff -u -r1.90 -r1.90.12.1 src/sys/arch/arm/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.