CVS commit: src/sys/arch/powerpc/pic

["Jared D. McNeill" <jmcneill%netbsd.org@localhost>]

Module Name:    src
Committed By:   jmcneill
Date:           Sat Feb 15 00:30:49 UTC 2025

Modified Files:
        src/sys/arch/powerpc/pic: intr.c

Log Message:
powerpc: Fix ci_ipending corruption with cascaded pics

A cascaded pic will register pic_handle_intr as its interrupt handler,
but interrupt handlers are called with MSR[EE] = 1. This breaks
assumptions in pic callbacks and can result in eg. corrupt ci_ipending
due to a read/modify/write of the field with nested interrupts.

Fix this by always clearing MSR[EE] at the top of pic_handle_intr.


To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/powerpc/pic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.