CVS commit: src/sys/arch/riscv/riscv

["Rin Okuyama" <rin%netbsd.org@localhost>]

Module Name:    src
Committed By:   rin
Date:           Thu Aug 24 05:46:55 UTC 2023

Modified Files:
        src/sys/arch/riscv/riscv: riscv_machdep.c

Log Message:
riscv: cpu_setmcontext: Do not unconditionally update tp register

Conserve tp register for _UC_CPU and update later if _UC_TLSBASE is
specified. This is what powerpc does, which also uses a general
purpose register for TLS pointer.

Found by tests/lib/libpthread/t_swapcontext:swapcontext1, which
successfully passes now.


To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/riscv_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.