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CVS commit: src/sys/arch/riscv/include



Module Name:    src
Committed By:   simonb
Date:           Fri Nov 11 01:18:32 UTC 2022

Modified Files:
        src/sys/arch/riscv/include: sysreg.h

Log Message:
The supervisor status register is the native word width, not fixed
at 32 bits.


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/sysreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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