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CVS commit: src/sys/arch/x86/x86



Module Name:    src
Committed By:   riastradh
Date:           Sat Aug 27 20:40:03 UTC 2022

Modified Files:
        src/sys/arch/x86/x86: db_memrw.c

Log Message:
x86/db_memrw.c: Mark db_read_bytes, db_write_bytes __noubsan.

These intentionally do loads and stores that may be misaligned, which
are fine on this x86-specific code.  Should avoid double-panic in
disassembler on panic with UBSan enabled.


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/x86/db_memrw.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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