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CVS commit: src/sys



Module Name:    src
Committed By:   andvar
Date:           Wed Mar 16 10:08:02 UTC 2022

Modified Files:
        src/sys/arch/mips/ralink: ralink_eth.c
        src/sys/dev/pci: if_jme.c

Log Message:
s/watchog/watchdog in comment and log message, one wording fix in comment.


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/ralink/ralink_eth.c
cvs rdiff -u -r1.50 -r1.51 src/sys/dev/pci/if_jme.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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