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CVS commit: src/sys/dev/pci
Module Name: src
Committed By: jakllsch
Date: Thu Apr 30 14:04:55 UTC 2020
msk(4): actually moderate interrupts from the Yukon 2 Status BMU
Previously the interrupt moderation enable register was being programmed
with sk(4)-style enable bits, none of which matched the significant
interrupt sources of the Yukon 2 we enable.
To generate a diff of this commit:
cvs rdiff -u -r1.107 -r1.108 src/sys/dev/pci/if_msk.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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