CVS commit: src/usr.sbin/cpuctl/arch

["SAITOH Masanobu" <msaitoh%netbsd.org@localhost>]

Module Name:    src
Committed By:   msaitoh
Date:           Mon Mar  5 05:50:37 UTC 2018

Modified Files:
        src/usr.sbin/cpuctl/arch: i386.c

Log Message:
- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
  this change doesn't decode perfectly.  Tested with Gemini Lake. It has
  two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
  printed yet:

        cpu0: ITLB 1 4KB entries 48-way
        cpu0: DTLB 1 4KB entries 32-way
        cpu0: L2 STLB 8 4MB entries 4-way

  Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.


To generate a diff of this commit:
cvs rdiff -u -r1.80 -r1.81 src/usr.sbin/cpuctl/arch/i386.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.