CVS commit: src/sys/arch/arm/cortex

To: source-changes%NetBSD.org@localhost
Subject: CVS commit: src/sys/arch/arm/cortex
From: "Nick Hudson" <skrll%netbsd.org@localhost>
Date: Fri, 15 May 2015 10:57:55 +0000

Module Name:    src
Committed By:   skrll
Date:           Fri May 15 10:57:55 UTC 2015

Modified Files:
        src/sys/arch/arm/cortex: a9_mpsubr.S

Log Message:
Make sure TLB is invalidated and ACTLR.SMP is set on ARM A15.  ACTLR.SMP
enables the processor to receive instruction cache, BTB and TLB main-
tenance operations from other processors


To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/a9_mpsubr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

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